1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of forming a gate electrode on a semiconductor device and a device incorporating same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the channel length of a transistor also increases “short-channel” effects, almost by definition, as well as “edge effects” that are relatively unimportant in long channel transistors. Short-channel effects include, among other things, an increased drain-source leakage current when the transistor is supposed to be switched “off.” This leakage is believed to be due to an enlarged depletion region relative to the shorter channel length. One of the edge effects that may influence transistor performance is known as Miller capacitance. The Miller capacitance is an overlap capacitance that arises because the conductive gate electrode almost invariably overlaps with a conductive portion of either the more heavily-doped source/drain regions or the less heavily-doped source/drain extension regions, if present, of a conventional transistor.
As shown in FIG. 1, for example, a conventional transistor 10 may be formed on a semiconducting substrate 12, such as doped silicon. The transistor 10 is comprised of a gate electrode 16 formed above a gate oxide 14 that is formed above the surface 13 of the semiconducting substrate 12. The gate electrode 16 and the gate oxide 14 may be separated from doped source/drain regions 18 of the transistor 10 by dielectric spacers 20. The dielectric spacers 20 may be formed above doped source/drain extension regions 19. As shown in FIG. 1, shallow trench isolation regions 25 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown).
The extension regions 19 are typically provided to reduce the magnitude of the maximum channel electric field found close to the source/drain regions 18 of the transistor 10, and, thereby, to reduce the associated hot-carrier effects. The lower (or lighter) doping of the extension regions 19, relative to the doping of source/drain regions 18 of the transistor 10, one typically lower or lighter by at least a factor of two or three, which reduces the magnitude of the maximum channel electric field found close to the doped source/drain regions 18 of the transistor 10, but increases the source-to-drain resistances of the extension regions 19.
As shown in FIG. 1, typically there are overlap regions where the edges 21 of the gate electrode 16 overlap with the edges 23 of the extension regions 19. The typical amount of overlap may be about 200 Å, for example. These overlap regions of the drain region and the gate electrode give rise to the Miller capacitance. As the overall dimensions of the transistor 10 are reduced, the Miller capacitance becomes a more dominant factor, particularly affecting the switching speed of the transistor 10. For example, when the transistor 10 is in an “off” state, there may be some residual charge stored in the overlap regions primarily due to the Miller capacitance. This “Miller charge” must be discharged before the transistor 10 may be switched from the “off” state to an “on” state, slowing down the switching speed. Similarly, the Miller capacitance in the overlap regions must be charged up again with the “Miller charge” after the transistor 10 is switched from the “on” state to the “off” state, further slowing down the switching speed.
The present invention is directed to a method and device that solves or at least reduces some or all of the aforementioned problems.